The present invention relates to an improved level-shifter for use in a memory circuit in which a large number of data lines operate in parallel in synchronization with a clock signal on a semiconductor chip, such as an image memory, a synchronous dynamic random-access memory (SDRAM), or a static random-access memory (SRAM) or in a microprocessor for performing parallel data processing, to a semiconductor integrated circuit using the improved level-shifter, and to control methods thereof.
A conventional level-shifter for shifting the amplitude level of an input signal so as to produce an output signal of a different amplitude level is disclosed in Japanese Laid-Open Patent Publication No. 4-211515 (by Nakagome et al. of Hitachi Ltd.). Below, a description will be given to the above prior art with reference to FIGS. 27 and 28.
FIG. 27(a) shows a clock-synchronization-type level-shifter and FIG. 27(b) illustrates the operation thereof. In FIG. 27(a) are shown: synchronizing signals CLK(3) and XCLK(2) (clock signals); an input signal Vin(11) prior to level shifting; a High level power source VH(90) after level shifting; a Low level power source VL(91) after level shifting; and a precharge power source VM(9) having an intermediate power-source potential between the above High level potential VH and Low level potential VL.
Next, the operation of the level-shifter will be described with reference to FIG. 27(b). When a PMOSFET(5) and an NMOSFET(6) are turned ON controlled by the clock signals CLK and XCLK, inverting operation is enabled so that the input Vin(11) is inverted and fetched. For example, if the Vin (11) is on the level of the power-source potential Vcc, the output has a Low level value represented by VL(91). Subsequently, when the above clock signals CLK and XCLK are inverted, the above PMOSFET(5) and NMOSFET(6) are turned OFF, while a PMOSFET(12) and an NMOSFET(9) are turned ON, so that the output is connected to the above precharge power source VM(9) and precharged to the intermediate potential. If the foregoing operation, forming one cycle, is repeatedly performed afterwards, the above input Vin(11) is inverted in every cycle and the output is also inverted. In the foregoing operation, variations in output level become (VH-VM) and (VM-VL), which are smaller than a variation in input level of (Vcc-Vss). Briefly, the amount of charge required for charging or discharging the parasitic capacitance CD(10) of the output node Vout is satisfactorily reduced. Since the amount of charge is determined by the product of a variation in the potential of the capacitance and the capacitance value, if the ratio of the amplitude level of an input to that of the output becomes 1/10, e.g., due to the level-shifter, the amount of charge required for charging and discharging the above output node also becomes 1/10. Compared with the case where level shifting is not performed, a reduction in power consumption by one order of magnitude can be achieved.
Next, a generator of the above power sources VH(90) and VL(91) which have been shifted in level is shown in FIG. 28. The generator is disposed on the same chip as the PMOSFET(6) and the like are disposed. As shown in the drawing, the generator has typically adopted a system for controlling the output transistor of a power-source circuit by a current-mirror-type output in which the potential obtained through resistance division by means of resistors R1, R2, and R3 is used as a reference potential. The voltage levels of the power sources VH(90) and VL(91) can arbitrarily be determined by adjusting the ratio among the above resistances R1, R2, and R3.
In the above internal power-source circuit shown in FIG. 28, however, it is necessary to supply a power-source current at low resistance to a driver for driving a line with a large capacitance. Accordingly, the above current mirror and output transistor increase in size so that the resistors R1, R2, R3, and R4 for generating the reference potential cannot be composed of resistors with high resistance values. As a result, the total sum of through currents IDC1 and IDC2 is increased to the order of several milliamperes, so that the disadvantage of uselessly increased power consumption is caused.
If the above conventional disadvantage is considered in terms of power consumption, the power consumption of the level-shifter in FIG. 27 becomes Ptoal=P1+P2. Here, the P2 is determined by the product of the current consumed in driving the wiring capacitance with an amplitude after level shifting and an amplitude voltage after level shifting. On the other hand, the above P1 represents the power consumed uselessly by the internal power-source circuit when it reduces voltage in generating the internal voltages VH and VL. The power consumption P1 is determined by the product of the current consumed in driving the wiring capacitance with the amplitude after level shifting and the amount of voltage (Vcc-VH+VL) reduced by the above internal power-source circuit. If the amount of the reduced voltage is large, i.e., if the output amplitude value is to be set smaller, the useless power consumption P2 is further increased.
Moreover, since 64-bit data lines, 128-bit data lines, or 256-bit data lines operate in parallel on the same chip in an image memory or the like, power consumption amounts to the value obtained by multiplying the above-mentioned power consumption by the number of bits, which is considerably large as a whole.
In the level-shifter shown in FIG. 27(a), the delay time between the change in the input Vin(11) caused in synchronization with the clock signal and the production of the output is represented by td1 shown in FIG. 27(b). The delay time td1 is primarily determined by the time required by the input to become lower and higher than the above power-source potentials VH(90) and VL(91) by the threshold voltages of the above PMOSFET(4) and NMOSFET(7), respectively. The power-source potentials VH(90) and VL(91) are the source potentials of the above PMOSFET(4) and NMOSFET(7) serving as the input gates. However, if the value of the power-source potential VH(90) is further reduced and the value of the power-source potential VL(91) is further increased in order to further reduce the output amplitude, the above PMOSFET(4) and NMOSFET(7) are turned ON only when the input approaches the lower potential Vss or the higher potential Vcc furthermore. Consequently, the delay time td1 is disadvantageously increased.
To prevent power dissipation due to the above internal power-source circuit, Japanese Laid-Open Patent Publication No. 4-302463 (by Takashima et al. of Toshiba Corporation) discloses a technique as illustrated in FIG. 29(a). With the technique, circuits 500 each showing an identical power-source current varying characteristic with respect to elapsed time, i.e., circuits 500 each having the same resistance in the ON state are connected in series between the power source Vcc and the ground line Vss so that the terminal voltage placed effectively on each of the circuits becomes half the power-source voltage Vcc. In other words, by connecting in series the circuits having equal power-source currents at each point of elapsed time as shown in FIGS. 29(a) and 29(b), i.e., by connecting in series the circuits having equal internal resistances in the ON state, each of the circuits 500 causes a voltage drop, while performing its intrinsic circuit operation, thereby performing the same function as performed by the above first conventional internal power-source circuit.
However, the above prior art of FIG. 29 is disadvantageous in that, if the power-source currents for the respective circuits are not equal at each point of elapsed time, the voltage determined by resistive division varies, so that the effective terminal voltages of the respective circuits vary. Moreover, since the power-source current for each of the circuits should be supplied by the ground current of its one-stage upper circuit, the current cannot be reused if the condition as shown in FIG. 29(b) is not satisfied, i.e., if the power-source currents I1 and I2 and ground currents I1X and I2X of the respective circuits 500 are not equal at each point of elapsed time. If a consideration is given to the sense amplifying operation of simultaneously restoring the potentials of individual bit lines which consume a large current in a DRAM, e.g., transistors with different functions are generally varied in size and in wiring resistance so that a time difference is automatically produced between charging operation accompanied by the flow of the power-source current and discharging operation accompanied by the flow of the ground current, thus preventing through currents from the power sources of the respective circuits to the ground. Therefore, it is impossible to equalize the charging currents and discharging currents of the respective circuits at each point of elapsed time without increasing the through currents. To cause the upper-stage and lower-stage circuits 500 to operate identically, it is necessary to supply a current from an additional circuit to the lower-stage circuit 500. Hence, it can be concluded that the prior art is still disadvantageous in that it uselessly consumes more current than is needed to drive the wiring capacitance.